The present invention relates to semiconductor device manufacturing, and more particularly to methods of fabricating multi-mesa metal oxide semiconductor field effect transistor (MOSFET) devices using damascene gate processing. The present invention is also directed to multi-mesa MOSFET structures that are formed by the inventive methods.
In recent years, there has been an interest in increasing the integration density of integrated circuits (ICs). This interest is driven by the requisite for ICs having low-power dissipation, higher performance, increased circuit functionality and reduced fabrication cost. Power dissipation may be reduced by lower operation voltages that may require the geometry of the IC to be scaled down to achieve a desired performance. As geometries scale down, conductor length and parasitic capacitance decrease resulting in a decrease in signal propagation time. Furthermore, there are certain economic benefits of reduced processing cost resulting in the formation of a greater number of circuits on a single wafer or chip. However, as active devices are scaled to smaller dimensions, the device voltage must also be scaled down in order to provide a device that is reliable. Therefore, scalability of devices is constrained by the competing consideration of device performance and reliability.
In some circumstances, scaling of other types of devices to smaller sizes may have a deleterious effect on performance, particularly when the capacitance coupling effects are relied upon for device operability. FETs, which typically rely on alteration of conduction characteristics of a device channel in a semiconductor body by a capacitively coupled electrical field, when scaled to extremely small lateral dimensions, do not exhibit scalability of drive voltages, particularly in conduction threshold voltage (Vt). In fact, it is sometimes quite difficult to avoid increasing the Vt for a given off-current because the sub-threshold slope degrades with higher doping concentrations; higher doping concentration is typically required to reduce short channel effects because of the limits on the minimum thickness of the gate dielectric material. Additionally, reduced size limits the gate voltage (Vg) that can be applied to the device without breakdown and the lack of scalability in Vt reduces the available overdrive voltage (Vgxe2x88x92Vt) with a consequent reduction of available on-current of the device. Hence, existing bulk complementary metal oxide semiconductor (CMOS) technologies cannot be extended into very low operating voltages (on the order of less than 1.5 V).
To avoid the above-mentioned limitation with existing CMOS technologies, very-low temperature operation and silicon-on-insulator (SOI) structures have been proposed in an attempt to reduce Vt. However, the use of low operation temperatures in CMOS devices imposes server limitations on such devices including, for example, the possibility of using the same as a portable device, as well as the increased cost of operating such a CMOS device. Also, packaging reliability may arise with using low operation temperature CMOS devices. SOI devices, on the other hand, suffer from floating body effects and the cost of manufacturing the SOI structure itself.
In addition to the above proposals, a very narrow channel MOSFET structure has been developed in order to improve sub-threshold slope and high conduction current; See, for example, IBM Technical Bull. Vol. 34, No. 12, pp. 101-102 (May 1992) entitled xe2x80x9cCorner Enhanced Field-Effect Transistorxe2x80x9d. In that prior art disclosure, corner conduction effects, which are generally considered to be parasitic at unavoidable edges of the channel, were exploited such that the corners dominate over the conduction in the remaining of the channel. This principal was extended, as described in the IBM Technical Bull. to a so-called multi-mesa structure by repeated conformal deposition and anisotropic etching of alternating layers of nitride and polysilicon which serve to fill the area between shallow trench isolation (STI) regions and form a plurality of narrow channels extending from the source to the drain of the transistor.
The fabrication of multi-mesa structures using the above processing steps of repeated deposition and etching is extremely expensive and, in some circumstances, compromises manufacturing yields. Further, corner dominated conduction implies high-levels of mesa doping to suppress conduction in other areas besides the corner regions. The prior art multi-mesa device also suffers from disproportionately high gate/input capacitance since significant portions of the area of the gate do not correspond to regions which significantly contribute to the conduction of the device.
Another approach to forming a similar multi-mesa device is disclosed, for example, in IBM Technology Bull. Vol. 34, No. 10A (March 1992), pp. 472-473. In this disclosure, slits are etched into a channel region formed in an SOI or bulk structure such that each slit essentially forms two back-to-back FETs, with the thickness of the channel layers defining the channel width. In this prior art method, the above problems with SOI structures are not obviated. Moreover, the slit and intervening channel size of the prior art structure is limited by minimum feature sizes obtainable with current lithography; limiting the minimum xe2x80x9cfootprintxe2x80x9d in which the transistor can occupy.
U.S. Pat. No. 5,675,164 to Brunner, et al. provide a multi-mesa structure having sub-lithographic mesa widths and periodicity. The multi-mesa structure disclosed in Brunner, et al. is formed using a subtractive gate etching process which includes the steps of: exposing a pattern of lines on a photoresist, said pattern of lines having a pitch that is less than one-half micron; etching grooves of sub-lithographic width forming a grooved surface including mesa structures; forming an oxide on said grooved surface; and applying a gate electrode over the oxide.
One drawback of subtractive gate etching processes such as disclosed in the Brunner, et al. patent is that gate conductor stringers remain between the mesas. Furthermore, prior art subtractive gate etching processes do not permit channel doping in each mesa to be spaced away from the source/drain junctions edges, therefore, the prior art mesa structures have a relatively high drain electrical field associated therewith which serves to decrease the hot-carrier reliability and to increase the body charging effects of the device.
In addition to the above drawbacks with prior art methods of fabricating multi-mesa structures, prior art methods also have the following problems associated therewith: (i) The aspect ratio of the mesas (grooves) is limited because of the difficulty of delivering the same level of dopant using ion implantation throughout the depth of the source or drain, each of which is a single block of silicon and exposed only on the top for any doping method. (ii) The current drive distribution is highly non-uniform due to the non-uniform vertical source/drain doping profiles; and (iii) The use of a spacer for gate extension formation plugs up the mesas that need to be selectively etched out while protecting gate spacers.
According, there is a need for providing a new and improved method of fabricating multi-mesa FET structures that have improved electrical characteristics such as an improved sub-threshold slope, negligible back bias sensitivity, a high immunity to drain induced barrier lowering (DIBL), and a high current drive.
One object of the present invention is to provide a multi-mesa FET structure that has doping on the sidewalls of the mesa in the source and drain area.
Another object of the present invention is to provide a multi-mesa FET structure that provides a uniform level of source and drain doping across the entire width of current conduction, and thus, the inventive structure has a well-defined threshold voltage and good sub-threshold slope characteristics associated therewith.
Yet another object of the present invention is to provide a multi-mesa FET structure that enables a much higher level of current density per unit silicon area by enabling tall mesas, without limitation to the uniformity of doping across the source and the drain.
Still another object of the present invention is to provide methods of fabricating a multi-mesa FET structure using processing steps that eliminate gate conductor stringers between adjacent mesas.
An even further object of the present invention is to provide methods of fabricating a multi-mesa FET structure which allow for the independent doping of the gate conductor and the source/drain diffusion regions.
A yet other object of the present invention is to provide methods of fabricating a multi-mesa FET structure which exhibit improved electrical properties such as a sub-threshold slope that does not degrade, negligible back bias sensitivity, a high immunity to DIBL, and a high current drive.
Other objects of the present invention include: (i) methods of fabricating a multi-mesa FET structure that permit the use of high-k gate dielectrics and metallic gate conductors. The term xe2x80x9chigh-k dielectricsxe2x80x9d denotes a dielectric material having a dielectric constant of about 10 or greater; and (2) methods of fabricating a multi-mesa FET in which the channel doping in each mesa is spaced away from the source/drain junction edges thereby reducing the drain electrical field, improving hot-carrier reliability and reducing body charging effects.
These and other objects and advantages are obtained in the present invention by providing methods that employ either a damascene gate process or alternatively a damascene replacement gate process instead of conventional subtractive etching methods. Both methods of the present invention are capable of forming a multi-mesa FET that has source and drain regions formed in sidewall portions of each mesa. In some highly preferred embodiments of the present invention, uniform doping of the sidewall portions of each mesa region created is achieved by gas phase doping or plasma doping.
In accordance with one aspect of the present invention, a multi-mesa FET structure is provided that comprises:
a plurality of Si-containing mesa regions, each mesa region having sidewall surfaces that are doped so as to form source and drain regions;
a channel region in each of said mesa regions, said channel region electrically contacting said source and drain regions;
a gate dielectric located atop said channel region on a surface of each of said mesa regions; and
a gate conductor atop said gate dielectric.
The mesa regions of the present invention may be configured to form either nested mesa regions or mesa regions that are parallel to one another.
The Si-containing mesa region may be comprised of Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, Si/SiGeC or a Si-containing layer of a silicon-on-insulator (SOI) wafer. That is, the mesas may be formed of bulk Si, a Si alloy such as SiGe, SiGe, SiC, and SiGeC, bulk Si having either a Si or Si alloy formed thereon, or a SOI wafer.
The damascene gate embodiment of the present invention comprises the steps of:
providing a planar structure comprising a pad stack located atop a Si-containing layer;
removing portions of the pad stack to define at least one device aperture in said structure;
forming at least one mesa region comprising a portion of said Si-containing layer in said at least one device aperture, said at least one mesa region having sidewall portions;
forming a dielectric material having an opening that exposes a portion of said at least one mesa region;
forming a first gate region including a channel region, gate dielectric and gate conductor in said opening, said channel region being formed into said at least one mesa region, while said gate dielectric and gate dielectric being formed on said at least one mesa region;
removing said dielectric material about said gate region and forming spacers on exposed vertical sidewalls of said gate conductor; and
forming source and drain regions in said sidewall portions of said at least one mesa region.
The first embodiment of the present invention may also be used to form a plurality of mesa regions in a plurality of device apertures. When a plurality of mesa regions are formed, the method of the first embodiment of the present invention can form a predetermined number of first gate regions, each first gate region having the same polarity (i.e., NFET or PFET), on a predetermined number of mesa regions, and thereafter second gate regions having opposite polarity of the first gate regions (i.e., NFET or PFET) can be formed in other mesa regions.
In the second embodiment of the present invention, i.e., the damascene gate replacement embodiment, the inventive method includes the steps of:
providing a planar structure comprising a patterned pad stack located atop a surface of Si-containing layer, said patterned pad stack surrounded by shallow trench isolation regions which extend into said Si-containing layer;
lining said structure including said patterned pad stack with a nitride layer;
providing an oxide layer that is coplanar with a surface of said nitride layer that is located atop an upper surface of said patterned pad stack and removing said nitride layer and a portion of said patterned pad stack to form at least one device aperture;
forming at least one mesa region in said at least one device aperture, said at least one mesa region including sidewall portions;
forming a mesa fill material on a portion of said at least one mesa region;
forming source and drain regions in said sidewall portions of said at least one mesa region;
removing the mesa fill material to expose a portion of said at least one mesa region; and
forming a first gate region including a channel region, gate dielectric and gate conductor on said exposed portion of said at least one mesa region, said channel region being formed into said at least one mesa region, while said gate dielectric and gate dielectric being formed on said at least one mesa region.
The term xe2x80x9cmesa fill materialxe2x80x9d is used herein to denote a material that can reasonably fill spaces which are formed between each mesa region. Examples of suitable materials include amorphous Si or polysilicon.
The second embodiment of the present invention may also be used to form a plurality of mesa regions in a plurality of device apertures. When a plurality of mesa regions are formed, the method of the second embodiment of the present invention can form a predetermined number of first gate regions, each first gate region having the same polarity (i.e., NFET or PFET), on a predetermined number of mesa regions, and thereafter second gate regions having opposite polarity of the first gate regions (i.e., NFET or PFET) can be formed in other mesa regions.